As transistor and interconnect geometry's shrink, the number of transistors capable of being connected together to form circuits in an integrated circuit (IC) increases. Also, the speed at which these circuits operate increases. With these increases in density and speed, the power consumed by circuits in an IC increases. The power consumed by an IC, according to the present invention, is of two general types, (1) the power consumed during functional operation of the IC, and (2) the power consumed during test operation of the IC. The functional operation power is the power consumed by the IC when it is operating in a system, such as a digital signal processor (DSP) IC operating in a cellular telephone. The test operation power is the power consumed by the IC when it is being tested, for example by a wafer or IC tester. In some instances, the test operation power may be much greater than the functional operation power.
According to the present invention, the test operation power is the power consumed by the IC or die when it is tested using the well known scan test methodology. As mentioned, the test operation power consumed during scan testing can be much greater than the functional operation power. This is because potentially all circuit registers (latches or DFFs), which are configured into scan cells, may be simultaneously clocked to shift data in and out during test. This differs from functional operation mode, where all circuit registers are not typically clocked simultaneously. In scan test mode, clocking all or near all circuit registers simultaneously causes the combinational logic connected to the registers to be dynamically activated. Dynamically activating the combinational logic during scan operations can cause the circuit to consume a significant amount of power.